Factorial Experiment on Cmos - Mems Rie Post Processing

CMOS-MEMS is a promising approach to achieve integration of microelectromechanical structures with circuits by using foundry CMOS services coupled with post-CMOS processing. The most significant benefit is the low cost of manufacturing the mechanical structures with CMOS. We report suitable conditions for post-CMOS processing by reactive ion etching (RIE) to define the mechanical structures. Values of power, pressure and gas flows are determined which achieve acceptable mechanical integrity, electrical continuity, etch rate and selectivities of the metal etch mask over the CMOS dielectric materials. Results are presented from a Box-Behnken factorial experiment to achieve these goals. INTRODUCTION Our approach to the goal of low-cost monolithic integration of circuits with microelectromechanical systems (MEMS) is to fabricate microstructures directly out of the interconnect layers in a conventional CMOS process. Such a process utilizes only maskless post-CMOS fabrication steps. The top metal layer in the CMOS process is used as an etch mask during RIE to release microstructures[1] as illustrated in Fig. 1 (a). As shown in Fig. 1 (b) and (c), the etch is divided into 2 steps: CHF3/O2 anisotropic etch of dielectric layers to define the structures; SF6/O2 isotropic etch of silicon to release the structures. Composite mechanical structures can include one polysilicon layer, three metal layers and the inter-metal dielectric layers. The dry etch release steps avoid sticking problems usually associated with the wet etch processing. About 5:1 high-aspect-ratio of beams can be achieved in this process. In this paper, our concentration is on the isotropic etching of interconnect dielectric layers. There are some dramatic differences in using RIE of dielectrics in CMOS micromachining when compared with integrated-circuit (IC) processing[2][3]. First, for definition of microstructures, it is preferred to have no selectivity in the vertical etch direction between silicon dioxide, silicon nitride and Si, since the structure etch must go through a stack of various dielectric layers. However, the selectivity between these materials and the metal mask layer, specifically aluminum, should be kept high. Second, ion milling during RIE is significant because of the extremely long etch of the dielectric layers. This milling of the metal layer can cause loss of device dimension and electrical connection failure. As in IC processing, the directivity of etching is achieved in part by control of passivation on the sidewall[4]. Too much polymerization on the surface will slow down the etching and limit the smallest spacing that can be achieved; too little polymerization will not provide protection on the sidewall, causing the loss of critical dimension. Third, electrical connection failures can result from the etch, mostly at vias connecting different metal layers. Failures are caused by two mechanisms as shown in Fig. 2: one is the removal of metal layer inside the vias which results in an open circuit at the sidewall of the vias; the second is lateral etching of refractory metal layers which exist above and below each aluminum layer in the submicron CMOS process.